Automatic test pattern generation (“ATPG”) was developed to explicitly test each gate and path in an integrated circuit (“IC”) design. As ICs have become larger and more complex, the amount of logic to be tested per input/output test pin has increased dramatically.
Test Compression is a technique used as part of a Design For Test (“DFT”) method to reduce the time and cost of testing integrated circuits. Straightforward application of scan techniques can result in large vector sets with corresponding long tester time and memory requirements. Test Compression takes advantage of the small number of significant values (care bits) techniques to reduce test data and test time, by decompressing the scan input on chip and compressing the test output. This technique allows highly compressed test stimuli to be applied from low-pin count testers and compressed test responses to be measured.
Scan channels are typically loaded by shifting them into the design registers 1 bit per clock cycle and thus, the longer the scan channels the more time it takes to load. The loading and unloading of long scan channels is not a very efficient use of tester time. A Test decompressor allows compressed test stimuli to be loaded from a small number of tester pins to a large number of very short internal scan channels; thereby reducing the test loading time. On the output side the short scan channels feeding a test compressor can reduce the time taken to unload the test response and store it on the tester for comparison.
The effectiveness of Test Compression can be degraded if the scan elements capture unknown logic states (“X-states”). X-states can occur for a variety of reasons, such as: (1) ATPG cannot accurately model certain logic modules and the un-modeled logic gets captured at a scan element (e.g., scan flip-flop), (2) internal three-state logic that could go to high-Z (i.e., high impedance), (3) uninitialized non-scan flip-flop/latches that cannot be reset prior to scan test application, (4) unknown RAM output (e.g., output of RAM may be unknown if not all of the RAM bits have time to get to logical “0” after a chip powers on), (5) a third-party vendor does not provide enough data to determine all of the possible outputs after a chip is powered on and, thus, X-states have to be assumed for the undetermined outputs, (6) some of the gates being tested are fed by analog logic (i.e., which does not use logical “1s” and “0s”), and (7) at-speed delay tests in which not all of the paths can meet the desired timings. Further, contrary to full-scan designs, in which X-states can be easily detected and suppressed, a single X-state found within a compression environment will likely combine with other non X-states (i.e., known values) and, thus, corrupt those values before they can be observed at the output of the compression. As such, as the X-states are shifted through the compression logic, the compression efficiency is adversely affected, resulting in a higher pattern count and lower test coverage.
On-chip masking hardware overcomes the above-discussed “X-state” problem. Essentially, ATPG applies masking logic to ensure targeted faults are not corrupted by an X-state. The masking logic masks the captured X-state and ensures that the masked “X-state” is instead read as a known value (i.e., a logical “0” or “1”). Current masking hardware solutions include a “WIDE1” channel mask and a “WIDE2” channel mask. With a “WIDE1” channel mask, each scan channel tail is monitored by a single mask register bit to prevent X-value propagation into the compression logic; therefore providing the ability to mask the channel on a per scan cycle basis. With a “WIDE2” channel mask, each scan channel tail is monitored by two mask register bits, thus providing ATPG greater flexibility in suppressing the “X-states” from affecting compression. For both “WIDE1” and “WIDE2” channel masking, mask data is serially loaded to the mask register bits via the scan-in input pins. The loading time to serially load the mask register bits is equivalent to the number of compression channels N divided by the number of scan inputs M (i.e., N/M). Each scan-input M provides mask data for N/M mask register bits. In addition, because the required mask data for the mask register bits changes on a pattern-to-pattern basis, new mask data has to be loaded for each test pattern.
As the compression logic grows, the number of required mask register bits and, thus, loading time also increases (e.g., corresponding to an increase in scan channels). For example, for a compressed design with 8 scan-in inputs and 3200 channels, 400 clock cycles would be required to load all of the mask register bits for one pattern. Assuming that the scan channel length L is less than 400 (e.g., scan channel length L is less than 100), this means it would to take longer to load the mask data than to load the actual scan channel data. Accordingly, as the loading time for the mask data increases, the test time and total data volume (i.e., due to an increase in mask data storage volume) also increases, defeating one of the primary motivations for test compression, i.e., decreasing test time and total data volume.
As such, there is a need for an efficient method and system of loading mask data to the mask register bits without having to serially load the mask data via the scan-in inputs.